1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating a capacitor.
2. Description of the Related Art
Memory function of a Dynamic Random Access Memory (DRAM) is carried out by controlling the voltage applied to the source region of a metal oxide semiconductor (MOS) transistor. Applying the voltage to the MOS transistor motivates electrons of a capacitor to flow. In this manner, a read or a write operation is carried out. However, when the capacitor is operated, the electrons in the capacitor are in a non-equilibrium state. In this non-equilibrium state, current leakage easily occurs. Therefore, it is necessary to refresh the capacitor periodically.
The refresh frequency depends on the charge-storage ability of the capacitor. As the storage ability of the capacitor increase, the refresh frequency for the capacitor is decrease. Thus, increasing the storage ability of the capacitor has become a development trend.
There are several methods for increasing the storage capacity of the capacitor. The methods include improving dielectric material and conductive material, and increasing the surface area of the capacitor. In order to increase the surface area of the capacitor, a hollow, cylindrical electrode has been developed. The surface area of the hollow, cylindrical bottom electrode is increased by forming an opening in a conductive layer to form a bottom electrode. The sidewall of the opening provides additional surface area in the bottom electrode. In this method, in order to increase further the surface area of the bottom electrode of the capacity, a very thick conductive layer is required.
Typically, the conductive layer is formed by deposition, and it takes a long time to deposit a thick conductive layer. Therefore, the fabrication process is slow down. In addition, because the conductive layer is thick, the conductive layer easily forms a hollow, cylindrical bottom electrode with a high, thin wall. The high, thin wall of the hollow, cylindrical bottom electrode cracks and breaks easily. The quality of the capacitor thus is degraded. The product yield is decreased, as well.
Reference is made to FIG. 1, which further explains the above-described, conventional cylindrical bottom electrode of the capacitor in details.
In FIG. 1, a dielectric layer 102 in formed on the substrate 100. A node contact opening 104 is formed in the dielectric layer 102 to expose a portion of the substrate 100. A patterned conductive layer 106 is formed on the dielectric layer 102 to fill the node contact opening 104. An opening 108 is formed in the conductive layer 106 to make the conductive layer 106 hollow and cylindrical in shape. The patterned conductive layer 106 is used as a bottom electrode. There is a correlation between the thickness of the conductive layer 106 and the surface area of the bottom electrode layer. That is, as the thickness of the conductive layer 106 increases, the surface area of the bottom electrode increases. In order to obtain a large surface area of the bottom electrode, it is desirable to form a thick conductive layer 106 having a thickness of about 8000 angstroms. Therefore, it takes a long time to deposit the conductive layer 106. This, in turn, increases the fabrication time for forming a capacitor, so that the yield is decreased.
Additionally, if the conductive layer 106 is very thick, after a opening 108 is formed in the conductive layer, the hollow, the cylindrical conductive layer 106 is easily formed with a high, thick wall. The high, thin sidewall cracks and breaks easily. In this manner, the quality of the capacitor is degraded.